SLG47004開發(fā)板套件編程器的評估板-嵌入式-復(fù)雜邏輯器件（FPGA,CPLD）規(guī)格書PDF中文資料

? Two Programmable Bandwidth Op Amps

? 3-Op Amp Instrumentation Amplifier Function

(including Additional Internal Op Amp)

? Rail to Rail Input

? Low Quiescent Current

? Low Offset Voltage

? Analog Comparator Mode

? Optional Vref Voltage Connection for Input Pins

? Two 1024 Position Digital Rheostats

? User Defined Auto-Trim Option

? Manual Control Option

? I2C Control Option

? Potentiometer Mode

? Two Single-Pole/Single-Throw Analog Switches

? Voltage or Current Source/Sink Mode

? One Low Offset Chopper Comparator

? Two Low Power General Purpose ACMPs

? ACMP Sampling Mode

? Hysteresis with Independently-Selectable Thresholds

? Three Voltage References

? Two ACMP Vref Output Buffers

? One High Drive Buffer

? Thirteen Combination Function Macrocells

? Three Selectable DFF/LATCH or 2-bit LUTs

? One Selectable Programmable Pattern Generator or

2-bit LUT

? Seven Selectable DFF/LATCH or 3-bit LUTs

? One Selectable Pipe Delay or Ripple Counter or