STM32F103RET6中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

The STM32F103xx medium-density performance line family incorporates the high performance ARM Cortex?-M3 32-bit RISC core operating at a 72 MHz frequency, high speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced ommunication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN.

Features

* ARM 32-bit Cortex?-M3 CPU Core

– 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access

– Single-cycle multiplication and hardware division

* Memories

– 64 or 128 Kbytes of Flash memory

– 20 Kbytes of SRAM

* Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration