STM32U385CG中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

Features

Includes ST state-of-the-art patented technology.

Ultra-low-power

? 1.71 V to 3.6 V power supply

? -40 °C to +105 °C temperature range

? VBAT mode: supply for RTC, 32 x 32-bit backup registers

? 1.6 μA Stop 3 mode with 8-Kbyte SRAM

? 2.2 μA Stop 3 mode with full SRAM

? 3.8 μA Stop 2 mode with 8-Kbyte SRAM

? 4.5 μA Stop 2 mode with full SRAM

? 9.5 μA/MHz Run mode @ 3.3 V (While(1) SMPS step-down converter mode)

? 13 μA/MHz Run mode @ 3.3 V/48 MHz (CoreMark? SMPS step-down

converter mode)

? 16 μA/MHz Run mode @ 3.3 V/96 MHz (CoreMark? SMPS step-down

converter mode)

? Brownout reset (BOR) in all modes except shutdown

Arm? 32-bit Cortex?-M33 CPU with TrustZone? and FPU

ART Accelerator

? 8-Kbyte instruction cache allowing 0-wait-state execution from flash and

external memories: frequency up to 96 MHz, MPU, 144 DMIPS and DSP

instructions

Power management

? Embedded regulator (LDO) and SMPS step-down converter supporting switch

on-the-fly and voltage scaling

Benchmarks

? 1.5 DMIPS/MHz (Dhrystone 2.1)

? 387 CoreMark?(4.09 CoreMark?/MHz)

? 500 ULPMark?-CP

? 117 ULPMark?-CM

? 202000 SecureMark?-TLS

Memories

? 1-Mbyte flash memory with ECC, 2 banks read-while-write

? 256 Kbytes of SRAM including 64 Kbytes with hardware parity check

? OCTOSPI external memory interface supporting SRAM, PSRAM, NOR,

NAND, and FRAM memories

Security and cryptography

? Arm? TrustZone? and securable I/Os, memories, and peripherals

? Flexible life cycle scheme with RDP and password protected debug

? Root of trust due to unique boot entry and secure hide protection area (HDP)

? Secure firmware installation (SFI) from embedded root secure services (RSS)

? Secure data storage with hardware unique key (HUK)

? Secure firmware upgrade

? Support of Trusted firmware for Cortex?M (TF-M)

? Two AES coprocessors, one with side channel attack resistance (SCA) (SAES)

? Public key accelerator, SCA resistant

? Key hardware protection

? Attestation keys

? HASH hardware accelerator

? True random number generator, NIST SP800-90B compliant

? 96-bit unique ID

? 512-byte OTP (one-time programmable)

? Antitamper protection

Clock management

? 4 to 50 MHz crystal oscillator

? 32.768 kHz crystal oscillator for RTC (LSE)

? Internal 16 MHz factory-trimmed RC (±1 %)

? Internal low-power RC with frequency 32 kHz or 250 Hz (±5 %)

? 2 internal multispeed 3 MHz to 96 MHz oscillators

? Internal 48 MHz with clock recovery

? Accurate MSI in PLL-mode and up to 96 MHz with 32.768 kHz, 16 MHz, or 32 MHz crystal oscillator

General-purpose inputs/outputs

? Up to 82 fast I/Os with interrupt capability most 5 V-tolerant and up to 14 I/Os with independent supply

down to 1.08 V

Up to 15 timers and 2 watchdogs

? 1x 16-bit advanced motor?control, 3x 32?bit and 3x 16?bit general purpose, 2x 16?bit basic, 4x low?power

16?bit timers (available in Stop mode), 2x watchdogs, 2x SysTick timer

? RTC with hardware calendar, alarms, and calibration

Up to 19 communication peripherals

? 1 USB 2.0 full-speed controller

? 1 SAI (serial audio interface)

? 3 I2C FM+(1 Mbit/s), SMBus/PMBus?

? 2 I3C (SDR), with support of I2C FM+ mode

? 2 USARTs and 2 UARTs (SPI, ISO 7816, LIN, IrDA, modem), 1 LPUART

? 3 SPIs (6 SPIs including 1 with OCTOSPI + 2 with USART)

? 1 CAN FD controller

? 1 SDMMC interface

? 1 audio digital filter with sound-activity detection

12-channel GPDMA controller, functional in Sleep and Stop modes (up to Stop 2)

Up to 21 capacitive sensing channels

? Support touch key, linear, and rotary touch sensors

Rich analog peripherals (independent supply)

? 2× 12-bit ADC 2.5 Msps, with hardware oversampling

? 12-bit DAC module with 2 D/A converters, low-power sample and hold, autonomous in Stop 1 mode

? 2 operational amplifiers with built-in PGA

? 2 ultralow-power comparators

CRC calculation unit

Debug

? Development support: serial-wire debug (SWD), JTAG, Embedded Trace Macrocell? (ETM)

All packages are ECOPACK2 compliant.