TMS320C40GFL60集成電路（IC）的DSP（數(shù)字信號(hào)處理器）規(guī)格書(shū)PDF中文資料

TMS320C40GFL60屬于集成電路（IC）的DSP（數(shù)字信號(hào)處理器）。由美國(guó)德州儀器公司制造生產(chǎn)的TMS320C40GFL60DSP（數(shù)字信號(hào)處理器）數(shù)字信號(hào)處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對(duì)連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號(hào)處理等應(yīng)用。

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Highest Performance Floating-Point Digital

Signal Processor (DSP)

– ’320C40-60:

33-ns Instruction Cycle Time,

330 MOPS, 60 MFLOPS,

30 MIPS, 384M Bytes/s

– ’320C40-50:

40-ns Instruction Cycle Time

– ’320C40-40:

50-ns Instruction Cycle Time

Six Communications Ports

Six-Channel Direct Memory Access (DMA)

Coprocessor

Single-Cycle Conversion to and From

IEEE-754 Floating-Point Format

Single Cycle, 1/x, 1/

Source-Code Compatible With TMS320C3x

Single-Cycle 40-Bit Floating-Point,

32-Bit Integer Multipliers

Twelve 40-Bit Registers, Eight Auxiliary

Registers, 14 Control Registers, and Two

Timers

IEEE 1149.1? (JTAG) Boundary Scan

Compatible

Two Identical External Data and Address

Buses Supporting Shared Memory Systems

and High Data-Rate, Single-Cycle

Transfers:

– High Port-Data Rate of 120M Bytes/s

(’C40-60) (Each Bus)

– 16G-Byte Continuous

Program/Data/Peripheral Address

Space

– Memory-Access Request for Fast,

Intelligent Bus Arbitration

– Separate Address-Bus, Data-Bus, and

Control-Enable Pins

– Four Sets of Memory-Control Signals

Support Different Speed Memories in

Hardware

325-Pin Ceramic Grid Array (GF Suffix)

Fabricated Using 0.72-mm Enhanced

Performance Implanted CMOS (EPICE)

Technology by Texas Instruments (TIE)

Software-Communication-Port Reset

NMI With Bus-Grant Feature

Separate Internal Program, Data, and DMA

Coprocessor Buses for Support of Massive

Concurrent Input/Output (I/O) of Program

and Data Throughput, Maximizing

Sustained Central Processing Unit (CPU)

Performance

On-Chip Program Cache and

Dual-Access/Single-Cycle RAM for

Increased Memory-Access Performance

– 512-Byte Instruction Cache

– 8K Bytes of Single-Cycle Dual-Access

Program or Data RAM

– ROM-Based Boot Loader Supports

Program Bootup Using 8-, 16-, or 32-Bit

Memories or One of the Communication

Ports

IDLE2 Clock-Stop Power-Down Mode

5-V Operation