UPD16340中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

· Circuit configuration switched by the IBS pin between three 32-bit bi-directional shift registers and six 16-bit bidirectional shift registers.

· Data control with transfer clock (external) and latch

· High-speed data transfer (fMAX. = 40 MHz MIN. at data latch)

(fMAX. = 25 MHz MIN. at cascade connection)

· High withstand output voltage (80 V, +50/–75 mA MAX.)

· 5-V CMOS input interface

· High withstand voltage CMOS structure