UPD44165362BF5-E35-EQ3-A中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

廠商型號	UPD44165362BF5-E35-EQ3-A
功能描述	18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
文件大小	464.51 Kbytes
頁面數(shù)量	37 頁
生產(chǎn)廠商	Renesas Technology Corp
企業(yè)簡稱	RENESAS【瑞薩】
中文名稱	瑞薩科技有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-5-8 20:24:00
人工找貨	UPD44165362BF5-E35-EQ3-A價格和庫存，歡迎聯(lián)系客服免費人工找貨

Features

? 1.8 ± 0.1 V power supply

? 165-pin PLASTIC BGA (13 x 15)

? HSTL interface

? PLL circuitry for wide output data valid window and future frequency scaling

? Separate independent read and write data ports with concurrent transactions

? 100 bus utilization DDR READ and WRITE operation

? Two-tick burst for low DDR transaction size

? Two input clocks (K and K#) for precise DDR timing at clock rising edges only

? Two output clocks (C and C#) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

? Internally self-timed write control

? Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

? User programmable impedance output (35 to 70 Ω)

? Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

? Simple control logic for easy depth expansion

? JTAG 1149.1 compatible test access port