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UPD98412中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

UPD98412
廠商型號(hào)

UPD98412

功能描述

MOS INTEGRATED CIRCUIT

文件大小

607.72 Kbytes

頁(yè)面數(shù)量

66 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-26 21:21:00

UPD98412規(guī)格書(shū)詳情

FEATURES

? Conforms to ATM FORUM UNI Version 3.1 & Traffic Management 4.0

? Realizes all switch functions with a single chip

? Non-blocking type with switch capacity of 1.5G bps

? UTOPIA Level2 interface allowing you to select bit widths

(4 ports ′ 8 bits, 2 ports ′ 8 bits + 1 port ′ 16 bits, 2 ports ′ 16 bits)

? Various polling modes for UTOPIA Level2 interface

? Can switch 30 logical ports

? Multi-speed (622M bps, 155M bps, 52M bps, 25M bps, etc.)

? Microprocessor connecting port can be set for signaling processing and OAM cell processing

? Supports 16K/32K/64K uni-cast VP/VC and 1K/2K/4K multi-cast VP/VC

? Shared buffer architecture using standard SRAM

? Cell buffer capacity: 12.8K/25.6K/51.2K cells

? Supports four QOS classes (CBR, VBR, ABR, UBR)

? ABR traffic control (binary mode)

? Supports EPD (Early Packet Discard) and PPD (Partial Packet Discard)

? +3.3-V single power source (directly connectable with +5-V TTL level signals)

? Test function: Supports JTAG (IEEE 1149.1)

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