VS1053中文資料VLSI數(shù)據(jù)手冊PDF規(guī)格書

Features

 Decodes

Ogg Vorbis;

MP3 = MPEG 1 & 2 audio layer III (CBR

+VBR +ABR);

MP1/MP2 = layers I & II optional;

MPEG4/ 2 AAC-LC(+PNS),

HE-AAC v2 (Level 3) (SBR + PS);

WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps);

General MIDI 1 / SP-MIDI format 0 files;

FLAC with software plugin;

WAV (PCM + IMA ADPCM)

 Encodes Ogg Vorbis w/ software plugin

 Encodes stereo IMA ADPCM / PCM

 Streaming support for MP3 and WAV

 EarSpeaker Spatial Processing

 Bass and treble controls

 Operates with a single 12..13MHz clock

 Can also be used with a 24..26MHz clock

 Internal PLL clock multiplier

 Low-power operation

 High-quality on-chip stereo DAC with no

phase error between channels

 Zero-cross detection for smooth volume

change

 Stereo earphone driver capable of driving

a 30

load

 Quiet power-on and power-off

 I2S output interface for external DAC

 Separate voltages for analog, digital, I/O

 On-chip RAM for user code and data

 Serial control and data interfaces

 Can be used as a slave co-processor

 SPI flash boot for special applications

 UART for debugging purposes

 New functions may be added with software

and up to 8 GPIO pins

 Lead-free RoHS-compliant package

Description

VS1053b is an Ogg Vorbis/MP3/AAC/WMA/

FLAC/WAVMIDI audio decoder as well as an

PCM/IMA ADPCM/Ogg Vorbis encoder on a

single chip. It contains a high-performance,

proprietary low-power DSP processor core

VS_DSP4, data memory, 16 KiB instruction

RAM and 0.5+ KiB data RAM for user applications

running simultaneously with any builtin

decoder, serial control and input data interfaces,

up to 8 general purpose I/O pins,

an UART, as well as a high-quality variablesample-

rate stereo ADC (mic, line, line + mic

or 2line) and stereo DAC, followed by an

earphone amplifier and a common voltage buffer.

VS1053b receives its input bitstream through

a serial input bus, which it listens to as a

system slave. The input stream is decoded

and passed through a digital volume control

to an 18-bit oversampling, multi-bit, sigmadelta

DAC. The decoding is controlled via a

serial control bus. In addition to the basic decoding,

it is possible to add application specific

features, like DSP effects, to the user

RAM memory.

Optional factory-programmable unique chip

ID provides basis for digital rights management

or unit identification features.