ADN2812

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERALDESCRIPTION TheADN2812providesthereceiverfunctionsofquantization,signalleveldetect,andclockanddatarecoveryforcontinuousdataratesfrom12.3Mb/sto2.7Gb/s.TheADN2812automaticallylockstoalldatarateswithouttheneedforanexternalreferenceclockorprogramming

ADN2812

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serialdatainput:12.3Mb/sto2.7Gb/s ExceedsSONETrequirementsforjittertransfer/generation/tolerance Quantizersensitivity:6mVtypical Adjustableslicelevel:±100mV Patentedclockrecoveryarchitecture Lossofsignal(LOS)detectrange:3mVto15mV Independentslice

ADN2812

連續(xù)速率12.3 Mb/s至2.7 Gb/s時(shí)鐘和數(shù)據(jù)恢復(fù)IC，集成限幅放大器

ADN2812可提供下列接收器功能：量化、信號(hào)電平檢測(cè)、時(shí)鐘和數(shù)據(jù)恢復(fù)，適用于從12.3 Mb/s到2.7 Gb/s的連續(xù)數(shù)據(jù)速率。它可自動(dòng)鎖定至所有數(shù)據(jù)速率，而無(wú)需外部參考時(shí)鐘或編程。該器件滿足所有的SONET抖動(dòng)要求，包括抖動(dòng)傳遞、抖動(dòng)產(chǎn)生和抖動(dòng)容差。所有規(guī)格均相對(duì)于?40°C至+85°C環(huán)境溫度而言，除非另有說(shuō)明。 ?????????????????????????????????????\n\n 該器件配合PIN二極管和TIA前置放大器，可以實(shí)現(xiàn)高度集成的低成本、低功耗光纖接收器。\n\n 當(dāng)輸入信號(hào)電平降至用戶可調(diào)閾值以下時(shí)，接收器前端信號(hào)丟失(LOS)檢測(cè)電路會(huì); ? 串行數(shù)據(jù)輸入：12.3 Mb/s至2.7 Gb/s\n\n? 超過(guò)SONET抖動(dòng)傳遞/產(chǎn)生/容差要求\n\n? 量化器靈敏度：6 mV（典型值）\n\n? 可調(diào)限幅電平：±100 mV\n\n? 取得專利的時(shí)鐘恢復(fù)架構(gòu)\n\n? 信號(hào)丟失(LOS)檢測(cè)范圍：3 mV至15 mV\n\n? 獨(dú)立限幅電平調(diào)整和LOS檢測(cè)器\n\n? 無(wú)需參考時(shí)鐘\n\n? 失鎖指示器\n\n? 通過(guò)I2C 接口訪問(wèn)可選特性\n\n? 單電源供電：3.3 V\n\n? 低功耗：750 mW（典型值）;

ADN2812_V01

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serialdatainput:12.3Mb/sto2.7Gb/s ExceedsSONETrequirementsforjittertransfer/generation/tolerance Quantizersensitivity:6mVtypical Adjustableslicelevel:±100mV Patentedclockrecoveryarchitecture Lossofsignal(LOS)detectrange:3mVto15mV Independentslice

ADN2812ACP

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERALDESCRIPTION TheADN2812providesthereceiverfunctionsofquantization,signalleveldetect,andclockanddatarecoveryforcontinuousdataratesfrom12.3Mb/sto2.7Gb/s.TheADN2812automaticallylockstoalldatarateswithouttheneedforanexternalreferenceclockorprogramming

ADN2812ACP-RL

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERALDESCRIPTION TheADN2812providesthereceiverfunctionsofquantization,signalleveldetect,andclockanddatarecoveryforcontinuousdataratesfrom12.3Mb/sto2.7Gb/s.TheADN2812automaticallylockstoalldatarateswithouttheneedforanexternalreferenceclockorprogramming

ADN2812ACP-RL7

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERALDESCRIPTION TheADN2812providesthereceiverfunctionsofquantization,signalleveldetect,andclockanddatarecoveryforcontinuousdataratesfrom12.3Mb/sto2.7Gb/s.TheADN2812automaticallylockstoalldatarateswithouttheneedforanexternalreferenceclockorprogramming

ADN2812ACPZ

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery

GENERALDESCRIPTION TheADN2812providesthereceiverfunctionsofquantization,signalleveldetect,andclockanddatarecoveryforcontinuousdataratesfrom12.3Mb/sto2.7Gb/s.TheADN2812automaticallylockstoalldatarateswithouttheneedforanexternalreferenceclockorprogramming

ADN2812ACPZ

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serialdatainput:12.3Mb/sto2.7Gb/s ExceedsSONETrequirementsforjittertransfer/generation/tolerance Quantizersensitivity:6mVtypical Adjustableslicelevel:±100mV Patentedclockrecoveryarchitecture Lossofsignal(LOS)detectrange:3mVto15mV Independentslice

ADN2812ACPZ-RL

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery

GENERALDESCRIPTION TheADN2812providesthereceiverfunctionsofquantization,signalleveldetect,andclockanddatarecoveryforcontinuousdataratesfrom12.3Mb/sto2.7Gb/s.TheADN2812automaticallylockstoalldatarateswithouttheneedforanexternalreferenceclockorprogramming