SLG47115開發(fā)板套件編程器的評估板-嵌入式-復雜邏輯器件（FPGA,CPLD）規(guī)格書PDF中文資料

Features

? Two Power Supply Inputs:

? 2.5 V (±8 ) to 5.0 V (±10 ) VDD

? 5.0 V (±10 ) to 24.0 V (±10 ) VDD2

? Two High Voltage High Current Drive GPOs

? Full Bridge Driver Option

? Dual/Single Half Bridge Driver Option

? Slew Rate Modes:

? Motor Driver Mode

? Pre-Driver (MOSFET Driver) Mode

? High Drive GPOs with Sleep Function

? Low RDS(ON) High-side + Low-side resistance = 0.5

W typical

? 3 A Peak, 1.5 A RMS per Full Bridge[1]

? Current up to 3 A Peak, 1.5 A RMS per GPO/Half

Bridge and up to 6 A Peak, 3 A RMS for two HV

GPOs Connected in Parallel[1]

? Integrated Over Current/Short

Circuit/Undervoltage-Lockout Protections

? SENSE Input that is connected to the Current

Comparator for Current Control

? Fault Signal Indicator (OCP/UVLO/TSD/)

? Differential Amplifier with Integrator and Comparator

for Motor Speed Control Function

? Current Sense Comparator with Dynamical Vref Mode

? Two High-Speed General Purpose ACMPs

? Modes: UVLO, OCP, TSD, Voltage Monitor,

Current Monitor

? One Voltage Reference (Vref) Output

? Five Multi-Function Macrocells